(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method to detect and identify diagonal or horizontal bridging between two DRAM capacitors.
(2) Description of the Prior Art
Semiconductors typically comprise numerous and complex semiconductor devices in addition to electrical components such as capacitors, resistors, diodes and the like that function in cooperation with the semiconductor devices. The art has long known numerous interacting technologies and numerous semiconductor materials that are used to create semiconductor components. Applied for this purpose are processing steps such as depositing layers of material, the shaping of deposited layers by for instance creating openings or interconnect lines in conductive layers, creating regions of different conductivity by means of ion impurity implantation, creating surface regions of low-sheet resistivity for optimum connectivity, etc. For many of these processing steps optimum processing conditions are required. This not only for the creation of the desired device feature but to in addition assure that the semiconductor material that is used for the process is deposited in a controlled manner and without causing undesirable side effects, such as the occurrence of salicided stringers during the process of salicidation. One of the side-effects of a semiconductor processing steps is the diffusion of deposited materials into surrounding layers of dielectric, for instance the diffusion of a deposited layer of copper into surrounding Intra Level Dielectric. Methods are known in the industry to prevent such diffusion such as for instant the application of a barrier layer across the trench or opening into which the copper is deposited. The material of the barrier layer is selected such that the copper is prevented from diffusion from the opening into which the copper is deposited. Multiple techniques are further known to prevent undesired ion diffusion. As an example of this can be cited the creation of Lightly Doped Diffusion (LDD) regions adjacent to gate electrodes, which eliminate the effects of intense concentrations of electromagnetic fields in the interface between the gate electrode and the surface of the substrate over which the gate electrode is created. Metals, which have been deposited for the creation of interconnecting lines or contact plugs, is particularly prone to diffusion. Metal diffusion most readily results in disturbing the lattice structure of the surrounding semiconductor material, most particularly the silicon of the silicon substrate over which semiconductor devices and features are created. Further processing, which frequently requires high temperature processing, can further aggravate the crystalline disturbance, modifying relatively simple and concentrated imperfections to the level of crystalline disturbances that may have a serious negative effect on overall devices performance and reliability. Since these crystalline imperfections are in most cases not observable during the process of creating semiconductor devices, the device or a sub-component of the device must be tested either at intermittent points during the processing cycle or after the processing cycle has reached a phase where the process can be advantageously interrupted for device testing. In addition, testing may provide test results which are difficult to correlate with actual deficiencies in the semiconductor structure, which further makes it difficult to correlate particular processing steps with the results of the testing and with particular imperfections in the created device or device features. In view of the frequently extended period of time that is required to create more complex semiconductor devices, it becomes even more urgent to establish clear testing procedures that clearly identify particular and well identifiable device deficiencies and that further correlate the testing with processing steps that most likely are the cause of the device deficiencies.
The industry has over the years used a number of techniques to control the frequently extended processing sequence that is required to create semiconductor devices. It is unacceptable to create these devices in one uninterrupted processing stream without validating the process of the device creation at particular points before the device processing sequence is completed. This approach has been implemented by processing multiple wafers in one identical processing stream and by extracting at critical points within the processing stream one or more of these wafers for testing. It is clear that this approach is not commensurate with maximizing semiconductor device throughout, since the wafers that are extracted in this manner are frequently not re-joined with the main stream of wafer processing. Also, it is difficult to make the processing increment between the points where wafers are extracted small enough so that individual processing steps can be isolated and the therefrom potentially resulting device defects can be identified. If for instance two processing steps are applied, such as the deposition and etching of a layer followed by annealing at high temperatures the etched layer of semiconductor material, the heating step may be the essential cause and contributor to the device defect that is identified. The testing however at this stage does not necessarily identify the heating step as being the cause of the device defect. The process is further complicated by even minute variations in processing conditions, for instance variations in density or energy of ion impurity implantations or small variations in the thickness of a deposited layer of semiconductor material. Further complicating the process of device testing is the fact that semiconductor wafers have been increasing in size, this in order to create more semiconductor chips from one wafer thus reducing the cost per device.
Imperfections in a crystalline structure are most frequently created in regions of high stress within the structure or in regions where impurities have been introduced into the molecular structure of the crystal. Frequently these imperfections can be eliminated by high temperature annealing even though, if improperly applied, high temperature annealing can further aggravate the crystalline imperfection. High stress regions for instance are sharp transitions of one surface into another such as at the bottom of a trench that is created for Shallow Trench Isolation regions or trenches created for the creation of interconnect lines. Special processing steps are frequently required to eliminate these sharp transitions or to create, for instance, trench openings that have nearly vertical sidewalls.
Semiconductor devices and the functions that are performed by these devices can generally be divided into functions of data manipulation or logic functions and functions of data storage. Functions of data manipulation are mostly related to digital data manipulation but can also comprise functions of analog data manipulation. Functions of data storage provide data retention capabilities that are performed by semiconductor memory devices. Two types of memory devices can be identified, that is memory functions that retain data in storage cells from which the data can only be read (Read Only Memories or ROM""s) and memory functions whereby the data cannot only be read but can also be altered (Random Access Memories or RAM""s).
Random Access Memories memory devices are created using a number of different approaches. This results in creating different types of RAM devices such as the Dynamic RAM (DRAM) devices, which use capacitors as the storage medium and which are therefore, due to the non-permanent nature of the capacitive storage, periodically refreshed, and Static RAM (SRAM) devices, which depend on the presence of a power source for the retention of the stored data. DRAM memories offer advantages of economy of construction and of relatively high storage capabilities and have therefore attracted most of the attention in the semiconductor industry.
Capacitors are critical components of RAM devices and can be divided in a number of different types of capacitors, dependent on and reflecting types of construction of the capacitor and the materials that are used in the construction of the capacitors. Known for instance are Metal Oxide Metal (MOM) capacitors and types of capacitors that are identified based on the materials that are used for the electrodes of the capacitors, such as polysilicon-silicon, polysilicon-polysilicon of metal-metal capacitors.
Capacitors that are an integral part of RAM devices can further be identified by the geometry or construction of the capacitor. One such construction provides a stacked capacitor. The memory cell under this arrangement comprises one transfer gate transistor and one stacked type capacitor. The transfer gate transistor comprises a pair of source/drain regions formed in a surface of a silicon substrate and a gate electrode (word line) that is formed on the surface of the silicon substrate with an insulation layer interposed therebetween. The stacked type capacitor comprises an underlying electrode (storage electrode) which extends from a position above the gate electrode to a position above a field isolation film, a part of the capacitor is connected to one of the source/drain regions of the gate electrode. A dielectric layer is formed on a surface of the underlying electrode and an upper electrode (cell plate) is formed on a surface of a dielectric layer. A bit line is formed on the capacitor with an interlayer insulation layer interposed therebetween, the bit line is connected to the other source/drain regions of the transfer gate transistor through a bit line contact portion. The stacked type capacitor is characterized in that capacitance of a capacitor is assured by providing the main part of the capacitor extending above the gate electrode and the field isolation film, this to increase an area where the electrodes of the capacitor are opposed to each other.
Another arrangement of a memory cell comprises a so-called cylindrical stacked type capacitor. A transfer gate transistor comprises a gate electrode (word line) with a-periphery that is covered with an insulation layer. A word line with a periphery that is covered with the insulation layer is formed on the surface of a shield electrode, which is formed on a surface of a silicon substrate with a shield gate insulation film interposed therebetween. An underlying electrode of the capacitor comprises a base portion (formed on a surface of an insulation layer covering surfaces of the gate electrode) and a word line with a cylindrical portion extending vertically and upwardly from the surface of the base portion in the form of a cylinder. A dielectric layer and an upper electrode are sequentially deposited on a surface of a lower electrode. The cylindrical portion of the capacitor can be used as a region for storing electric charges, enabling the capacitance of the capacitor to be increased without increasing the plane of the capacitor.
The invention addresses a testing procedure that is applied during the creation of DRAM devices, and more specifically addresses the presence of interconnects or bridging that may occur between adjacent capacitor openings. This bridging is an issue that, with the decreasing dimensions of devices and device features, takes on more urgency since the openings that must be created for the creation of capacitors are very closely spaced.
For purposes of understanding, the prior art cross section of FIG. 1 is first discussed. Shown in FIG. 1 is a cross section of a DRAM cell having two capacitors, the elements that are shown in cross section in FIG. 1 are the following:
10, the semiconductor substrate in and on the surface of which the DRAM cell is created
12, the regions of field oxide that electrically isolated the DRAM cell
14, a layer of pad oxide created over the active surface regions of substrate 10
16, the adjacent polysilicon gate electrodes (Metal Oxide Field Effect Transistors or MOSFET""s), gate electrodes 16 form the word lines of the DRAM cell
17, the bit line of the DRAM cell
18, the (common) drain of the two gate electrodes 16
20, the two source regions of the gate electrodes 16
22, word lines overlying the field oxide regions 12, these word lines 22 are connected to other, surrounding MOSFET devices that are located in an array above and below the plane of the cross cut that is shown in FIG. 1
24, a first layer of insulation typically comprising Inter Polysilicon (IPO) 26, a second layer of insulation typically comprising Inter Polysilicon (IPO)
28, the first or lower electrodes of the capacitors of the DRAM cell
30, the dielectric of the capacitors of the DRAM cell
32, the second or upper electrode of the capacitors of the DRAM cell
34, a layer of insulation of Inter Level Dielectric that protects the DRAM cell, and
36, the two stacked capacitors of the DRAM cell.
The first or lower electrodes 28 of the two capacitors 36 contact the source regions 20 of the adjacent gate electrodes 16, bit line 17 is connected to the common drain 18 of the gate electrodes 16. Typically deposited over layer 34 of ILD is a layer of metal (not shown) that is patterned and etched to further interconnect the DRAM cell as a first layer of metal. Prior to the deposition of this layer of metal openings are created through layer 34 in order to connect the layer of metal to the capacitors of the DRAM cell.
For purposes of better understanding, a top view of the DRAM cell of FIG. 1 is shown in FIG. 2. Key to this understanding is the realization that the cross section that is shown in FIG. 1 has been taken along the line 1-1xe2x80x2 of FIG. 2. Further highlighted in FIG. 2 are:
16, the adjacent polysilicon gate electrodes, which form the word lines of the DRAM cell
17, the bit line of the DRAM cell
19, the bit line of an adjacent DRAM cell (not shown in FIG. 1)
22, word lines overlying the field oxide regions 12
38, the active region in the surface of substrate 10 over which the polysilicon gate electrodes 16 and the storage capacitors 36 are created as shown in cross section in FIG. 1
39, two adjacent active regions (not shown in FIG. 1)
40, which is a contact region to an adjacent capacitor (not shown in FIG. 1) in an adjacent active region 39
44, which is the contact region of the bit line 17 of the two gate electrodes 16
42 and 46, which are the contact regions of the capacitors 36 to the two source regions 20 of the two gate electrodes 16.
The invention provides a new test methodology for the testing of DRAM cells and more specifically for the detection of bridging that can occur between adjacent DRAM capacitors.
U.S. Pat. No. 6,028,324 (Su et al.), U.S. Pat. No. 5,977,558 (Lee), U.S. Pat. No. 5,872,018 (Lee), U.S. Pat. No. 5,576,223 (Zeininger et al.) show related test structures.
A principle objective of the invention is to provide a method of determining bridging between adjacent capacitors of a DRAM cell.
Another objective of the invention is to provide a method of determining bridging between adjacent capacitors of a DRAM cell whereby this method allows for differentiating between horizontal bridging and diagonal bridging between adjacent capacitors.
In accordance with the objectives of the invention a new method is provided for the interconnection of bit lines in the test structure. The invention provides for the creation of a cross comb bit line design in the test structure which allows for the detection and identification of diagonal or horizontal bridging between two identifiable capacitors of DRAM structures.